Publications for Topic Computer Architecture

Domschitz, P.*; Schwarz, A.*: Aspekte der Ankopplung von Multimedia-Workstations an das B-ISDN. Beiträge zum GI/ITG Arbeitstreffen Verteilte Multimedia Systeme, Stuttgart, February 1993, pp. 48-57. [Show full record]

Domschitz, P.*; Lemppenau, W.*; Sauer, K.; Schwarz, A.*: Flexible Prototyping the Attachment of Multimedia-Workstations to a B-ISDN Demonstrator. Proceedings of the 6th IEEE Workshop on Local and Metropolitan Area Networks, San Diego, October 1993. [Show full record]

Schwarz, A.*; Domschitz, P.*: Aspects of the Adaptation of Multimedia-Workstations to B-ISDN. Proceedings of the 3rd Joint Workshop on High Speed Networks, Paris, March 1993. [Show full record]

Schwederski, T.; Schwarz, A.*; Bernath, E.: Performance and VLSI Design of a Single-Chip Network Switching Element with Central Memory Buffers. Proceedings of the 22nd International Conference on Parallel Processing, St. Charles, IL, August 1993. [Show full record]

Sailer, R.*; Federrath, H.; Jerichow, A.; Kesdogan, D.; Pfitzmann, A.: Allokation von Sicherheitsfunktionen in Kommunikationsnetzen. Mehrseitige Sicherheit in der Kommunikationstechnik; Verfahren, Komponenten, Integration, Addison-Wesley, Bonn, D, October 1997, pp. 325-357. [Show full record] / Download [PDF]

Keck, D.O.*; Jurczyk, M.: Parallel Discrete Event Simulation of Wormhole Routing Interconnection Networks. Proceedings of the 10th IASTED International Conference on Parallel and Distributed Computing and Systems, Las Vegas, October 1998, pp. 391-395. [Show full record] / Download [PS.GZ]

Keck, D.O.*; Jurczyk, M.: Traffic Control in Wormhole Routing Meshes under Non-Uniform Traffic Patterns. Proceedings of the 11th IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, November 1999, pp. 302-133-1-302-133-6. [Show full record] / Download [PS]

Trefz, M.; Dolzer, K.*: An Experimental On-board Multiservice Switch. Proceedings of the 5th European Conference on Satellite Communications, Toulouse, November 1999. [Show full record] / Download [PDF]

Feil, V.*; Gemkow, U.*; Stümpfle, M.: A vehicular software architecture enabling dynamic alterability of services sets. Proceedings of the 3rd IFIP/GI International Conference on Trends Towards a Universal Service Market (USM 2000), Munich, September 2000, pp. 152-163. [Show full record] / Download [PDF]

Macian, C.*; Domschitz, P.: Advanced IP classification techniques for a hybrid routing node in a DWDM metropolitan network. Proceedings of the European Conference on Networks and Optical Communications 1999 (NOC '99) Part 2: Core networks and network management, Stuttgart, June 2000. [Show full record] / Download [PDF]

Feil, V.*; Stümpfle, M.: Management-Aufgaben bei komponentenbasierten verteilten Systemen im Fahrzeug-Telematikbereich. Beiträge zur 12. GI/ITG Fachtagung Kommunikation in Verteilten Systemen (KiVS 2001), Hamburg, February 2001. [Show full record] / Download [PDF]

Feil, V.*: Resource management for constant bit rate streams in component-based distributed systems. Proceedings of the 20th IASTED International Conference on Applied Informatics, Symposium on Parallel and Distributed Computing and Networks, Innsbruck, February 2002, pp. 149-154. [Show full record] / Download [PDF]

Gloss, B.*; Kühn, P.J.*: Modellierung und Entwurf von Kommunikations-Infrastrukturen für orts- und kontextabhängige Dienste. Tagungsmappe zum DFG-Workshop Modelle, Werkzeuge und Infrastrukturen zur Unterstützung von Entwicklungsprozessen, Aachen, March 2002. [Show full record] / Download [PDF]

Meyer, M.*: An On-Chip Garbage Collection Coprocessor for Embedded Real-Time Systems. Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Hong Kong, August 2005, pp. 517-524. [Show full record] / Download [PDF]

Hofstee, P.; Necker, M.C.: Performance and memory bandwidth utilization for tree searches using tree fragmentation. Patent, No, December 2006. [Show full record]

Meyer, M.*: A True Hardware Read Barrier. Proceedings of the 2006 International Symposium on Memory Management, Ottawa, Ontario, June 2006, pp. 3-16. [Show full record] / Download [PDF]

Stanchina, S.*; Meyer, M.*: Mark-Sweep or Copying? A 'Best of Both Worlds' Algorithm and a Hardware-Supported Real-Time Implementation. Proceedings of the 2007 International Symposium on Memory Management, Montreal, October 2007. [Show full record] / Download [PDF]

Hauger, S.*; Scharf, M.*; Kögel, J.*; Suriyajan, C.: Quick-Start and XCP on a Network Processor: Implementation Issues and Performance Evaluation. Proceedings of the IEEE International Conference on High Performance Switching and Routing (HPSR 2008), Shanghai, May 2008. [Show full record] / Download [PDF]

Hauger, S.*: A Novel Architecture for a High-Performance Network Processing Unit: Flexibility at Multiple Levels of Abstraction. Proceedings of the IEEE International Conference on High Performance Switching and Routing (HPSR 2009), Paris, June 2009. [Show full record] / Download [PDF]

Hauger, S.*: Designing High-Speed Packet Processing Tasks at Arbitrary Levels of Abstraction - Implementation and Evaluation of a MIXMAP System. Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2009), Princeton, October 2009. [Show full record] / Download [PDF]

Hauger, S.*; Wild, T.; Mutter, A.*; Kirstädter, A.*; Karras, K.; Ohlendorf, R.; Feller, F.*; Scharf, J.*: Packet Processing at 100 Gbps and Beyond - Challenges and Perspectives. Beiträge zur 10. ITG Fachtagung Photonic Networks, Leipzig, May 2009, pp. 43-52. [Show full record] / Download [PDF]

Teuchert, D.; Hauger, S.*: A Pipelined IP Address Lookup Module for 100 Gbps Line Rates and beyond. Proceedings of the 15th Open European Summer School (EUNICE 2009), Barcelona, September 2009. [Show full record] / Download [PDF]

Hauger, S.*; Scharf, M.; Kögel, J.*; Suriyajan, C.: Evaluation of Router Implementations for Explicit Congestion Control Schemes. Journal of Communications, Vol. 5, No. 3, March 2010, pp. 197-204. [Show full record] / Download [PDF]

Horvath, O.*; Meyer, M.*: Fine-Grained Parallel Compacting Garbage Collection through Hardware-Supported Synchronization. 5th International Symposium on Embedded Multicore SoCs, San Diego, 2010. [Show full record] / Download [PDF]

Meyer, M.*: Prozessorarchitektur für exakte Zeigeridentifizierung. Patent, No EP 1 639 475 B1, September 2010. [Show full record]

Hauger, S.*: Architektur für flexible Paketverarbeitung in Hochgeschwindigkeitskommunikationsnetzen - Communication Networks and Computer Engineering Report No. 107. Dissertation, Universität Stuttgart, Informatik, Elektrotechnik und Informationstechnik, 2011. [Show full record] / Download [PDF]