Publication No 40015

Author(s)

Hauger, S.*

Title

Designing High-Speed Packet Processing Tasks at Arbitrary Levels of Abstraction - Implementation and Evaluation of a MIXMAP System

Topics

Broadband Networks; Computer Architecture

Methods

Systems Engineering; Computer Architecture

Keywords

NETWORK PROCESSOR; HIGH SPEED; ARCHITECTURE; BROADBAND; FAST PACKET SWITCHING; IMPLEMENTATION; MULTIPROCESSOR SYSTEM; PROGRAMMABLE LOGIC

Abstract

Packet processing systems of forthcoming high-speed network nodes demand extremely high processing rates, but also modularity and easy adaptability due to new or evolving protocols and services. As the fixed architecture and instruction set of current network processors sometimes hinders an efficient implementation of processing tasks, we introduced the MIXMAP architecture [at HPSR 2009] that is designed to offer programmability at multiple levels of abstraction. Now we describe the prototypical realization of this architecture showing its feasibility. Our results indicate that up to 170 million packets per second can be processed with this architecture using current FPGAs. By implementing packet processing tasks at register-transfer level and at software level, we validate the architecture's applicability and the bene?ts of implementing at an appropriate level of abstraction.

Year

2009

Reference entry

Hauger, S.
Designing High-Speed Packet Processing Tasks at Arbitrary Levels of Abstraction - Implementation and Evaluation of a MIXMAP System
Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2009), Princeton, October 2009

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