Publications with Method Computer Architecture

Meyer, M.*: A Novel Processor Architecture with Exact Tag-Free Pointers. Proceedings of the 2nd Workshop on Application Specific Processors, San Diego, California, December 2003, pp. 96-103. [Show full record] / Download [PDF]

Meyer, M.*: A Novel Processor Architecture with Exact Tag-Free Pointers. IEEE Micro, Vol. 24, No. 3, May 2004, pp. 46-55. [Show full record] / Download [PDF]

Stanchina, S.*; Meyer, M.*: Exploiting the Efficiency of Generational Algorithms for Hardware-Supported Real-Time Garbage Collection. Proceedings of the 22nd ACM Symposium on Applied Computing, SAC 2007, Seoul, March 2007. [Show full record] / Download [PDF]

Stanchina, S.*; Meyer, M.*: Mark-Sweep or Copying? A 'Best of Both Worlds' Algorithm and a Hardware-Supported Real-Time Implementation. Proceedings of the 2007 International Symposium on Memory Management, Montreal, October 2007. [Show full record] / Download [PDF]

Hauger, S.*; Scharf, M.*; Kögel, J.*; Suriyajan, C.: Quick-Start and XCP on a Network Processor: Implementation Issues and Performance Evaluation. Proceedings of the IEEE International Conference on High Performance Switching and Routing (HPSR 2008), Shanghai, May 2008. [Show full record] / Download [PDF]

Hauger, S.*: A Novel Architecture for a High-Performance Network Processing Unit: Flexibility at Multiple Levels of Abstraction. Proceedings of the IEEE International Conference on High Performance Switching and Routing (HPSR 2009), Paris, June 2009. [Show full record] / Download [PDF]

Hauger, S.*: Designing High-Speed Packet Processing Tasks at Arbitrary Levels of Abstraction - Implementation and Evaluation of a MIXMAP System. Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2009), Princeton, October 2009. [Show full record] / Download [PDF]

Hauger, S.*; Scharf, M.; Kögel, J.*; Suriyajan, C.: Evaluation of Router Implementations for Explicit Congestion Control Schemes. Journal of Communications, Vol. 5, No. 3, March 2010, pp. 197-204. [Show full record] / Download [PDF]

Horvath, O.*; Meyer, M.*: Fine-Grained Parallel Compacting Garbage Collection through Hardware-Supported Synchronization. 5th International Symposium on Embedded Multicore SoCs, San Diego, 2010. [Show full record] / Download [PDF]

Meyer, M.*: Prozessorarchitektur für exakte Zeigeridentifizierung. Patent, No EP 1 639 475 B1, September 2010. [Show full record]

Hauger, S.*: Architektur für flexible Paketverarbeitung in Hochgeschwindigkeitskommunikationsnetzen - Communication Networks and Computer Engineering Report No. 107. Dissertation, Universität Stuttgart, Informatik, Elektrotechnik und Informationstechnik, 2011. [Show full record] / Download [PDF]