Institute of Communication Networks and Computer Engineering (IKR) - Offered Student project topics

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Universität Stuttgart

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	Institute of Communication Networks and Computer Engineering (IKR)
	Offered Student project topics

All topics offered in the last few month


In the table below you find a list of all student project topics of the last few months giving an overview of the topics currently actual in the institute. The List of all currently offerend topics is a subset of this complete list.

Bachelor thesis and research thesis projects

Master thesis

DLT-Based Credit and Compensation System for Open-Source Resources
(Bachelor thesis No. 1046)

Entwurf und Implementierung einer virtuellen Speicherverwaltung für ein prototypisches Rechnersystem mit einem 64-Bit RISC-V Prozessor
(Bachelor thesis No. 1054)

Entwurf und Implementierung eines USB-Treiber-Frameworks für ein prototypisches Rechnersystem mit einem 64-Bit RISC-V Prozessor
(Bachelor thesis No. 1052)

Designing and Implementing a GNPy Wrapper for Increased Programmability
(Bachelor thesis No. 1045)

Spezifikation, Redesign und systematischer Test der Caches in einem superskalaren objektbasierten Prozessor in VHDL
(Bachelor thesis No. 1044)

Logic Design and Implementation for a PCI Express Graphics Card for an Experimental Object-Based Computer System in VHDL
(Bachelor thesis No. 1043)

Messung und Optimierung der Leistungsfähigkeit einer Linux-basierten Firewalls
(Bachelor thesis No. 1042)

Building a Julia App for Visualizing Multi-Domain Intent-Driven Operation
(Bachelor thesis No. 1041)

Design and Implementation of a PCI Express Root Complex for an experimental Object-Based Computer System
(Bachelor thesis No. 1040)

Entwurf und Implementierung eines Monitors für ein experimentelles objektbasiertes Rechnersystem
(Bachelor thesis No. 1039)

Entwurf und Implementierung eines Backends für einen Modell-Compiler mit SSA-basiertem Register-Allokator
(Bachelor thesis No. 1038)

Design and implementation of a modular input/output unit for peripherals of a 64-bit RISC-V processor
(Bachelor thesis No. 1036)

Development of a RISC-V emulator as a web application
(Bachelor thesis No. 1035)

Design und Implementierung von Peripherie- und Speicherkomponenten für ein experimentelles Rechnersystem
(Bachelor thesis No. 1034)

Entwicklung eines RISC-V Emulators in Java und Integration in ein bestehendes Framework für Prozessoremulatoren
(Bachelor thesis No. 1032)

Verkehrsmodellierung von Multimedia Streaming Diensten
(Bachelor thesis No. 1027)

Employing GNPy for planning Meshed Metro Optical Networks
(Bachelor thesis No. 1026)

Design and implementation of dynamic branch prediction mechanisms in a RISC-V processor
(Bachelor thesis No. 1025)

The potential role of IOTA in Distributed-Ledger Technology
(Bachelor thesis No. 1023)

Improvement of message exchange for the distributed dispatching of rail vehicles
(Bachelor thesis No. 1021)

Side channel attack sensibility of Logic-Locked cryptographic circuits
(Bachelor thesis No. 1020)

Entwurf und Implementierung eines hochverfügbaren Captive Portal
(Bachelor thesis No. 1017)

Extension of a Network Simulator for decentralized railway control
(Bachelor thesis No. 1016)

Intelligent energy management system based on the ARM Cortex M0 + platform
(Bachelor thesis No. 1015)

Implementation of a Link-State Routing Protocol
(Bachelor thesis No. 1014)

Flexible Network Simulator for Decentralized Railway Control
(Bachelor thesis No. 1013)