Publication No 40014

Author(s)

Mutter, A.*

Title

A Novel Hybrid Memory Architecture with Parallel DRAM for Fast Packet Buffers

Topics

Broadband Networks

Methods

Systems Engineering

Keywords

BUFFER; INPUT BUFFER; OUTPUT BUFFER; BUFFER DIMENSIONING; BUFFER MANAGEMENT; HIGH SPEED; ARCHITECTURE; IMPLEMENTATION; BROADBAND; PACKET SWITCHING

Abstract

High speed Internet routers and switches require fast packet buffer to hold packets during times of congestion. These buffers usually use a memory hierarchy that consist of expensive but fast SRAM and cheap but slow DRAM to meet both, speed and capacity requirements. A challenge building these packet buffers is to provide deterministic bandwidth guarantee under any traffic condition. We propose a novel hybrid packet buffer architecture with parallel DRAMs. Our approach reduces the amount of required SRAM compared to state-of-the-art architectures significantly, e. g., the tail SRAM by 47% for a 100Gbps line card using DDR3 SDRAM. Our architecture also applies packet aggregation and thereby minimizes the required DRAM and SRAM bandwidth and eliminates fragmentation. We are currently implementing the architecture on an FPGA and provide first results.

Year

2010

Reference entry

Mutter, A.
A Novel Hybrid Memory Architecture with Parallel DRAM for Fast Packet Buffers
Proceedings of the 11th International Conference on High Performance Switching and Routing (HPSR 2010), Dallas, June 2010

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