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Institute of Communication Networks and Computer Engineering (IKR)
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Project description |
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Bachelor thesis No. 1020
(Finished) [pdf]
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Side channel attack sensibility of Logic-Locked cryptographic circuits
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Methods
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Topics
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Measurements
Digital systems design
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Cryptography
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Description
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Background
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Logic Locking protects a circuit against potential attacks in the IC supply chain by inserting additional logic components into the circuit. A quite common symmetric cipher is the Advanced Encryption Standard (AES) which can be implemented as a circuit in hardware. Those cryptographic circuits must be protected against passive physical attacks like side-channel attacks, which can be done using masking.
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Problem Description
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The target of this thesis is to test if logic locking a masked cryptographic circuit weakens the security of the keys used in the circuit against side channel attacks. For this purpose, DOM-AES, a masked version of an AES-circuit will be tested with and without logic locking, and the ?Test Vector Leakage Assessment? (TVLA) will be used to test the circuits against side-channel attacks.
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Aquired Knowledge and Skills
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Design of digital cryptographic circuits protected against side-channel attacks (masking), VHDL/Verilog, synthesis of digital circuits, Xilinx FPGA tools, measurements, side-channel-attacks, Student?s t-test, statistics.
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Requirements
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Digital systems design
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Contact
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Dipl.-Ing. Matthias Meyer,
room 1.334 (ETI II),
phone 685-67975, [E-Mail]
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