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MICROSAR based Interprocess Communication in a Multicore-SoC for the Parallelization of CAN-Tasks
(Master thesis No. 1031)
Design of a Compiler Frontend for GoSUB, an Experimental variant of the Go Programming Language, and Implementation of the Frontend in GoSUB
(Master thesis No. 1058)
Qualitative Exploration and Modelling of IOTA Tangle and its Impact on the Network
(Master thesis No. 1057)
Development and Evaluation of Image-based Train Positioning Algorithms using Cameras in a Test Rig
(Master thesis No. 1056)
Design of a Compiler Frontend for GoSUB, an Experimental variant of the Go Programming Language, and Implementation of the Frontend in GoSUB
(Master thesis No. 1055)
Design and Implementation of an Ethernet Interface for an Experimental Object-Based Computer System
(Master thesis No. 1053)
"Fast Misprediction Recovery" for a Superscalar Object-Based Prozessor in VHDL
(Master thesis No. 1051)
Network Traffic Prediction with Machine Learning using Gaussian Processes
(Master thesis No. 1050)
Design and Implementation of a PCI Express Endpoint for an FPGA in VHDL to attach peripheral components to an Object Based Research Processor.
(Master thesis No. 1049)
Entwurf und Implementierung eines PCIe Transaction Layer Packet Generators mit Hilfe eines AMD FPGA mit integriertem ARM-Prozessor (SoC)
(Master thesis No. 1048)
Solving the Routing, Modulation, and Spectrum Assignment Problem using Reinforcement Learning
(Master thesis No. 1037)
Dimensioning a German Train IP-Optical Network with Integer Linear Programming
(Master thesis No. 1033)
MICROSAR based Interprocess Communication in a Multicore-SoC for the Parallelization of CAN-Tasks
(Master thesis No. 1031)
Network Pathfinding with Reinforcement Learning
(Master thesis No. 1030)
Design and Implementation of an Intent-Based Networking Framework on top of ONOS SDN Controller
(Master thesis No. 1024)
Traffic Prediction on Backbone Networks Using Gaussian Processes
(Master thesis No. 1022)
Implementation and Evaluation of a SDN-controlled Network Emulation with Containerized Network Elements
(Master thesis No. 1019)
Communication Mechanisms for Distributed Train Disposition Based on Swarm Intelligence
(Master thesis No. 1012)
Integration of a hardware based mechanism for control-flow integrity in a RISC-V processor
(Master thesis No. 1010)
Quantification of the Availability Compliance in Shared Path Protected Networks
(Master thesis No. 1007)
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