Publication No 40012

Author(s)

Mutter, A.*

Title

A Novel Hybrid SRAM/DRAM Memory Architecture for Fast Packet Buffers

Topics

Broadband Networks

Methods

Systems Engineering

Keywords

BUFFER DIMENSIONING; HIGH SPEED; ARCHITECTURE; BROADBAND; FAST PACKET SWITCHING

Abstract

This paper addresses the design of fast packet buffers for high speed Internet routers and switches. These buffers usually use a memory hierarchy that consist of expensive but fast SRAM and cheap but slow DRAM to meet both speed and capacity requirements. One challenge building these packet buffers is to provide worst-case bandwidth guarantees and fixed latencies, not to stall pipelines or to reduce throughput. My colleagues and I propose a novel packet buffer architecture along with a new memory management algorithm which reduces the amount of required SRAM compared to other architectures, e.g. by 73% for a 100Gbps system using DDR3-DRAM. Furthermore, our architecture scales well with line rate.

Year

2009

Reference entry

Mutter, A.
A Novel Hybrid SRAM/DRAM Memory Architecture for Fast Packet Buffers
Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2009), Princeton, October 2009

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