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Institute of Communication Networks and Computer Engineering (IKR)

IKR Publication No 36302

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Publication No 36302

Author(s)

Meyer, M.*

Title

A Novel Processor Architecture with Exact Tag-Free Pointers

Methods

Computer Architecture

Abstract

Garbage collection has become a major cornerstone of almost any modern object-oriented programming language, as it considerably increases programmer productivity and software quality. Along with the success of Java, the benefits of garbage collection advance to the area of embedded and real-time systems, thus posing new challenges to processor architects. This paper presents a novel RISC processor architecture that introduces the robustness stemming from garbage collection at the machine-code level. This is accomplished by an object-based architecture that maintains the invariant that (1) every pointer can be exactly identified, and (2) every pointer value is either null or uniquely associated with an existing object. The basic idea for ensuring this is to strictly separate pointers from ordinary data, thereby allowing for tag-free pointer identification. The architecture provides the basis for garbage collection in hardware that closely cooperates with the processor. The advantages of this configuration include low garbage collection overhead, low-cost synchronization of collector and application program, high robustness and hard real-time capabilities. A pipelined RISC processor conforming to the proposed architecture as well as a micro-coded hardware garbage collector have been realized on a single programmable logic device. A native Java bytecode compiler developed for the architecture facilitates the execution of large existing programs. Performance measurements on the prototype show that, despite the required synchronization, the real-time hardware garbage collector is significantly more efficient than a non-incremental 'stop-the-world' software garbage collector.

Year

2003

Reference entry

Meyer, M.
A Novel Processor Architecture with Exact Tag-Free Pointers
Proceedings of the 2nd Workshop on Application Specific Processors, San Diego, California, December 2003, pp. 96-103

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Authors marked with an asterisk (*) were IKR staff members at the time the publication has been written.